Robert Hancock wrote:
> Previously a device tree property was added to allow overriding the
> reference clock period parameter if the default value used was incorrect.
> However, there is another register field, GFLADJ_REFCLK_FLADJ, which
> reflects the fractional nanosecond portion of the reference clock
> period. Add a snps,ref-clock-fladj property to allow configuring this
> as well.
>
> On the Xilinx ZynqMP platform, the reference clock appears to always
> be 20 MHz, giving a clock period of 50 ns. However, the default value
> of GFLADJ_REFCLK_FLADJ was 1008 rather than 0 as it should have been,
> which prevented many USB devices from functioning properly. The
> psu_init code run by the Xilinx first-stage boot loader sets this
> value to 0, however when the controller is reset by the dwc3-xilinx
> layer, the incorrect default value is restored. This configuration
> property allows ensuring that the correct value is always used.
>
> Signed-off-by: Robert Hancock <robert.hancock@xxxxxxxxxx>
> ---
> drivers/usb/dwc3/core.c | 32 ++++++++++++++++++++++++++++++++
> drivers/usb/dwc3/core.h | 3 +++
> 2 files changed, 35 insertions(+)
>
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index f4c09951b517..6289fbcbad45 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -359,6 +359,34 @@ static void dwc3_ref_clk_period(struct dwc3 *dwc)
> }
>
>
> +/*
Use kernel doc style "/**"
> + * dwc3_ref_clk_fladj - Reference clock period (fractional portion) configuration
> + * GFLADJ_REFCLK_FLADJ contains the fractional portion of the reference clock
> + * period set in GUCTL_REFCLKPER.
It's not a direct "fractional portion" the way it's described here. It
may cause some confusion. Let's use the word adjustment to account for
the fractional portion that's calculated as below.
> + * Calculated as: ((125000/ref_clk_period_integer)-(125000/ref_clk_period)) * ref_clk_period
Note that ref_clk_period_integer is the value in GUCTL.REFCLKPER, and
the "ref_clk_period" is the period with fractional value.
> + * This value can be specified in the device tree if the default value is incorrect.
> + * Note that 0 is a valid value.
> + *
> + * @dwc3: Pointer to our controller context structure
> + */
> +static void dwc3_ref_clk_fladj(struct dwc3 *dwc)
> +{
> + u32 reg, reg_new;
I believe Felipe prefers to declare them in separate lines. Let's keep
it consistent as how we do it in for this driver.
> +
> + if (DWC3_VER_IS_PRIOR(DWC3, 250A))
> + return;
> +
> + if (!dwc->ref_clk_fladj_set)
> + return;
> +
> + reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
> + reg_new = reg & ~DWC3_GFLADJ_REFCLK_FLADJ_MASK;
> + reg_new |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, dwc->ref_clk_fladj);
> + if (reg_new != reg)
> + dwc3_writel(dwc->regs, DWC3_GFLADJ, reg_new);
> +}
> +
> +
> /**
> * dwc3_free_one_event_buffer - Frees one event buffer
> * @dwc: Pointer to our controller context structure
> @@ -1033,6 +1061,7 @@ static int dwc3_core_init(struct dwc3 *dwc)
>
> /* Adjust Reference Clock Period */
> dwc3_ref_clk_period(dwc);
> + dwc3_ref_clk_fladj(dwc);
>
> dwc3_set_incr_burst_type(dwc);
>
> @@ -1418,6 +1447,9 @@ static void dwc3_get_properties(struct dwc3 *dwc)
> &dwc->fladj);
> device_property_read_u32(dev, "snps,ref-clock-period-ns",
> &dwc->ref_clk_per);
> + if (!device_property_read_u32(dev, "snps,ref-clock-fladj",
> + &dwc->ref_clk_fladj))
> + dwc->ref_clk_fladj_set = true;
Please document it in the dwc3 DT file whenever we introduce a new property.
Also, do we need to add a new dwc->ref_clk_fladj_set? Can we just define
some default value for dwc->ref_clk_fladj as unspecified and have the
driver check against that (e.g. #define DWC3_REFCLK_FLADJ_UNSPECIFIED
0xffffffff).
Thanks,
Thinh
>
> dwc->dis_metastability_quirk = device_property_read_bool(dev,
> "snps,dis_metastability_quirk");
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index e1cc3f7398fb..650d4c2e7a67 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -388,6 +388,7 @@
> /* Global Frame Length Adjustment Register */
> #define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7)
> #define DWC3_GFLADJ_30MHZ_MASK 0x3f
> +#define DWC3_GFLADJ_REFCLK_FLADJ_MASK 0x3fff00
>
> /* Global User Control Register*/
> #define DWC3_GUCTL_REFCLKPER_MASK 0xffc00000
> @@ -1166,6 +1167,8 @@ struct dwc3 {
>
> u32 fladj;
> u32 ref_clk_per;
> + bool ref_clk_fladj_set;
> + u32 ref_clk_fladj;
> u32 irq_gadget;
> u32 otg_irq;
> u32 current_otg_role;
