Re: [PATCH v9 3/4] arm64: dts: qcom: sc7280: Add PCIe nodes for IDP board

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On 2021-09-29 02:22, Stephen Boyd wrote:
Quoting Prasad Malisetty (2021-09-28 06:55:49)
Enable PCIe controller and PHY for sc7280 IDP board.
Add specific NVMe GPIO entries for SKU1 and SKU2 support.

Signed-off-by: Prasad Malisetty <pmaliset@xxxxxxxxxxxxxx>
---
 arch/arm64/boot/dts/qcom/sc7280-idp.dts  |  9 ++++++
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 54 ++++++++++++++++++++++++++++++++
 arch/arm64/boot/dts/qcom/sc7280-idp2.dts |  9 ++++++
 3 files changed, 72 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
index 64fc22a..1562386 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
@@ -61,6 +61,15 @@
        modem-init;
 };

+&nvme_pwren_pin {
+       pins = "gpio19";
+};

This should move to the bottom in the "pinctrl" section.

+
+&nvme_3v3_regulators {
+       gpio = <&tlmm 19 GPIO_ACTIVE_HIGH>;
+       enable-active-high;

The enable-active-high can be in the idp.dtsi file? That doesn't seem to
change.

+};
+
 &pmk8350_vadc {
        pmr735a_die_temp {
                reg = <PMR735A_ADC7_DIE_TEMP>;
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index def22ff..5b5505f 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -31,6 +31,17 @@
                        linux,can-disable;
                };
        };
+
+       nvme_3v3_regulators: nvme-3v3-regulators {

Why plural? Isn't it a single regulator?

+               compatible = "regulator-fixed";
+               regulator-name = "VLDO_3V3";
+
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+
+               pinctrl-names = "default";
+               pinctrl-0 = <&nvme_pwren_pin>;
+       };
 };

 &apps_rsc {
@@ -220,6 +231,42 @@
        modem-init;
 };

+&pcie1 {
+       status = "okay";
+       perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>;
+
+       vddpe-3v3-supply = <&nvme_3v3_regulators>;
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie1_default_state>;
+};
+
+&pcie1_phy {
+       status = "okay";
+
+       vdda-phy-supply = <&vreg_l10c_0p8>;
+       vdda-pll-supply = <&vreg_l6b_1p2>;
+};
+
+&pcie1_default_state {

I thought the node would be split into a reset config node and a wake
config node. Is that not being done for some reason? The pinctrl-0 would
look like

	pinctrl-0 = <&pcie1_default_state>, <&pcie1_reset_n>, <&pcie1_wake_n>;

+       reset-n {
+               pins = "gpio2";
+               function = "gpio";
+
+               drive-strength = <16>;
+               output-low;
+               bias-disable;
+       };
+
+       wake-n {
+               pins = "gpio3";
+               function = "gpio";
+
+               drive-strength = <2>;
+               bias-pull-up;
+       };
+};
+
 &pmk8350_vadc {
        pmk8350_die_temp {
                reg = <PMK8350_ADC7_DIE_TEMP>;
@@ -489,3 +536,10 @@
                bias-pull-up;
        };
 };
+
+&tlmm {
+       nvme_pwren_pin: nvme-pwren-pin {
+               function = "gpio";
+               bias-pull-up;
+       };
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp2.dts b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts
index 1fc2add..0548cb6 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp2.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts
@@ -21,3 +21,12 @@
                stdout-path = "serial0:115200n8";
        };
 };
+
+&nvme_pwren_pin {
+       pins = "gpio51";
+};

The pin config can go to a pinctrl section at the bottom of this file?

Hi Stephen,

Thanks for the review and comments.

Sure, I will address all the comments and incorporate the changes in next version series.

Thanks
-Prasad
+
+&nvme_3v3_regulators {
+       gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>;
+       enable-active-high;
+};



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