Re: [PATCH 2/2] ARM: dts: qcom: ipq4019: add dwc3 arch spec compatible

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On Wed 08 Sep 14:33 CDT 2021, David Heidelberg wrote:

> To be compilant with qcom,dwc3 definition
>  - add compatible
>  - rename dwc3@ to usb@
> 
> No functional changes intended.
> 
> Signed-off-by: David Heidelberg <david@xxxxxxx>
> ---
>  arch/arm/boot/dts/qcom-ipq4019.dtsi | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
> index a3ae5458ac68..25b7e10537df 100644
> --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
> +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
> @@ -637,7 +637,7 @@ usb3_hs_phy: hsphy@a6000 {
>  		};
>  
>  		usb3: usb3@8af8800 {
> -			compatible = "qcom,dwc3";
> +			compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
>  			reg = <0x8af8800 0x100>;
>  			#address-cells = <1>;
>  			#size-cells = <1>;
> @@ -648,7 +648,7 @@ usb3: usb3@8af8800 {
>  			ranges;
>  			status = "disabled";
>  
> -			dwc3@8a00000 {
> +			usb@8a00000 {

As noted in a recent discussion, this causes the UDC name exposed in
sysfs to change. So even though it's contradicting the binding let's
keep it unchanged for now.

The compatible part looks good though, so can you please respin this
patch with that part only?

Thanks,
Bjorn

>  				compatible = "snps,dwc3";
>  				reg = <0x8a00000 0xf8000>;
>  				interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
> @@ -669,7 +669,7 @@ usb2_hs_phy: hsphy@a8000 {
>  		};
>  
>  		usb2: usb2@60f8800 {
> -			compatible = "qcom,dwc3";
> +			compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
>  			reg = <0x60f8800 0x100>;
>  			#address-cells = <1>;
>  			#size-cells = <1>;
> @@ -680,7 +680,7 @@ usb2: usb2@60f8800 {
>  			ranges;
>  			status = "disabled";
>  
> -			dwc3@6000000 {
> +			usb@6000000 {
>  				compatible = "snps,dwc3";
>  				reg = <0x6000000 0xf8000>;
>  				interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
> -- 
> 2.33.0
> 



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