Hello! On 13.04.2021 10:17, Artur Petrosyan wrote:
Updates the implementation of entering clock gating mode when core receives port suspend. Instead of setting the required bit fields of the registers inline, called the "dwc2_host_enter_clock_gating()" function. Signed-off-by: Artur Petrosyan <Arthur.Petrosyan@xxxxxxxxxxxx> --- drivers/usb/dwc2/hcd.c | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c index 27f030d5de54..e1225fe6c61a 100644 --- a/drivers/usb/dwc2/hcd.c +++ b/drivers/usb/dwc2/hcd.c
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@@ -3323,22 +3322,12 @@ int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) break; case DWC2_POWER_DOWN_PARAM_HIBERNATION: case DWC2_POWER_DOWN_PARAM_NONE: - default: - hprt0 = dwc2_read_hprt0(hsotg); - hprt0 |= HPRT0_SUSP; - dwc2_writel(hsotg, hprt0, HPRT0); - hsotg->bus_suspended = true; /* - * If power_down is supported, Phy clock will be suspended - * after registers are backuped. + * If not hibernation nor partial power down are supported,
s/not/neither/? MBR, Sergei
