RE: Question on clear_tt_buffer for not TDI but with built-in TT

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Hi, Alan,

> > > You have to explain more clearly how the Xilinx controller expects
to
> > > receive these messages.
> > >
> >
> > I am not sure whether it is possible. But a control message of
> > HUB_CLEAR_TT_BUFFER is expected to clear the tt buffers inside TT
for a
> > particular endpoint, just like the one in hub_clear_tt_buffer(). My
> > understanding is that this message will be addressed to the root
hub,
> > however, it will go through the TT, and get executed there.
> 
> Your understanding must be wrong or confused.  For instance, what
> device address do you think this message will be sent to?  Don't say
> address 0 -- that address is reserved for use by new devices before
> they have been enumerated.
> 
> Can you check up on this and find out the correct answer?
> 
> Alan Stern
> 
I checked and found that in Xilinx's Host controller case, the time that
the TT is enabled is because a FS device is directly connected. The TT
therefore knows the HS control transfer, HUB_CLEAR_TT_BUFFER, must be
for the TT itself. All traffic to downstream would be split transfers,
since the host controller is directly connected to a FS device. So, the
device address for the HS control transfer of HUB_CLEAR_TT_BUFFER is not
critical for the control message to reach the TT. The port address is
useful to find which port's TT. However, Xilinx's EHCI host controller
only has one port.

I do think this is not a pretty solution. I think we will hold this and
wait for a solution in Linux, and will adjust our hardware to that (we
are taking the advantage of FPGA).

Thanks,
Julie.

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