The 'reg' description and example have a 2nd register region for memory
mapped flash, but the schema says there is only 1 region. Fix this.
Cc: Mark Brown <broonie@xxxxxxxxxx>
Cc: Palmer Dabbelt <palmer@xxxxxxxxxxx>
Cc: Paul Walmsley <paul.walmsley@xxxxxxxxxx>
Cc: linux-spi@xxxxxxxxxxxxxxx
Cc: linux-riscv@xxxxxxxxxxxxxxxxxxx
Signed-off-by: Rob Herring <robh@xxxxxxxxxx>
---
Please ack, dependency for patch 5.
Documentation/devicetree/bindings/spi/spi-sifive.yaml | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/spi-sifive.yaml b/Documentation/devicetree/bindings/spi/spi-sifive.yaml
index 28040598bfae..fb583e57c1f2 100644
--- a/Documentation/devicetree/bindings/spi/spi-sifive.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-sifive.yaml
@@ -32,11 +32,10 @@ properties:
https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi
reg:
- maxItems: 1
-
- description:
- Physical base address and size of SPI registers map
- A second (optional) range can indicate memory mapped flash
+ minItems: 1
+ items:
+ - description: SPI registers region
+ - description: Memory mapped flash region
interrupts:
maxItems: 1
--
2.20.1
