On 2020-05-01 11:37, Mark Rutland wrote:
On Fri, May 01, 2020 at 09:05:00AM +0200, Greg KH wrote:
On Thu, Apr 30, 2020 at 04:19:22PM -0500, Jeremy Linton wrote:
> On arm64, and possibly other architectures, requesting
> IO coherent memory may return Normal-NC if the underlying
> hardware isn't coherent. If these pages are then
> remapped into userspace as Normal, that defeats the
> purpose of getting Normal-NC, as well as resulting in
> mappings with differing cache attributes.
What is "Normal-NC"?
Arm terminology for "Normal Non-Cacheable"; it might be better to say
something like:
On some architectures (e.g. arm64) an IO coherent mapping may use
non-cachable attributes if the relevant device is cache coherent.
is *not* cache coherent.
If userspace mappings are cacheable, these may not be coherent with
non-cacheable mappings. On arm64 this is the case for Normal-NC and
Normal (cacheable) mappings.
And to answer some of Greg's questions:
- This can show up on current HW that doesn't offer full IO coherency,
which is likely on low-end arm/arm64 systems.
- I guess nobody noticed this before as x86 is perfectly happy with
conflicting attributes for the same physical page, and there is
(wild guess) probably not that much userspace making use of shared
mappings between kernel and userspace using this interface.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
