On 14/06/2019 08:46, JC Kuo wrote: > PLLE hardware power sequencer has to be enabled after PEX/SATA > UPHY PLL's sequencers are enabled. > > tegra210_plle_hw_sequence_start() for XUSB PADCTL driver to enable > PLLE hardware sequencer at proper time. > > tegra210_plle_hw_sequence_is_enabled() for XUSB PADCTL driver to > check whether PLLE hardware sequencer has been enabled or not. I think that here to be clear about what is going on you should state that you are "adding the function tegra210_plle_hw_sequence_start() ..." Are these functions dependent upon clk_plle_tegra210_enable() already being called? I assume that there must be some dependency between the above functions and the existing plle enable function. If there is a dependency, how do you ensure the existing enable is already called? Cheers Jon -- nvpublic
