Hi Miquel,
I have only a few smallish remarks:
On ven., janv. 11 2019, Miquel Raynal <miquel.raynal@xxxxxxxxxxx> wrote:
> Marvell Armada 3700 SoC has two USB controllers, each of them being
> wired to an internal UTMI PHY. Add a driver to control them.
>
> Igal Liberman worked on supporting the PHY, I took the while 'register
> configuration' from his work and rewrote almost entirely the
> driver/bindings around it.
>
> Co-developed-by: Igal Liberman <igall@xxxxxxxxxxx>
> Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx>
> Signed-off-by: Igal Liberman <igall@xxxxxxxxxxx>
> ---
[...]
> diff --git a/drivers/phy/marvell/phy-mvebu-a3700-utmi.c b/drivers/phy/marvell/phy-mvebu-a3700-utmi.c
> new file mode 100644
> index 000000000000..97d8235d661d
> --- /dev/null
> +++ b/drivers/phy/marvell/phy-mvebu-a3700-utmi.c
> @@ -0,0 +1,297 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2018 Marvell
> + *
> + * Authors:
> + * Evan Wang <xswang@xxxxxxxxxxx>
> + * Miquèl Raynal <miquel.raynal@xxxxxxxxxxx>
If it is co-developed with Igal Liberman, shouldn't be added here too?
[...]
> +static int mvebu_a3700_utmi_phy_power_on(struct phy *phy)
> +{
> + struct mvebu_a3700_utmi *utmi = phy_get_drvdata(phy);
> + struct device *dev = &phy->dev;
> + int usb32 = utmi->caps->usb32;
> + int ret = 0;
> + u32 reg;
> +
> + if (!utmi)
> + return -ENODEV;
> +
> + /*
> + * Setup PLL. 40MHz clock used to be the default, bein 25MHz now.
bein?
> + * See "PLL Settings for Typical REFCLK" table.
[...]
> +
> + /* Wait for squetch calibration */
squetch?
Gregory
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
