Re: USB power fault question

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On Friday 24 April 2009, Kumar Gala wrote:
> I'm hopping someone here might be able to help me understand better  
> what a USB Power fault condition is as referenced in the USB ULPI PHY  
> specifications.
> 
> I'm trying to understand better under physical conditions a power  
> fault would be signaled to the PHY and possible to the USB host  
> controller.

You want me to look at the ULPI spec for you?  :)

The two power faults that come to mind are both host side:

 - One relates to the A_WAIT_VRISE transition, whereby
   VBUS must become valid within 100 msec after certain
   events.  In the best of all possible worlds, it's a
   nice gradual rise, no bumps.  More typically, it's
   got a current spike and becomes briefly invalid ...
   which *ought* to be just fine, since 100 msec hasn't
   yet elapsed, but silicon has been known to flake out.

 - A similar one relates to current spikes *after* that
   transition.  In those cases, overcurrent errors are
   perfectly reasonable to treat as errors.

In short, VBUS going invalid in states other than
the A_WAIT_VFALL transitions.

Now, look at the spec and tell me where I goofed.  ;)

- Dave

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