Check and configure TX/RX threshold for DWC_usb31. Update dwc3 structure
with new variables to store these threshold configurations.
Signed-off-by: Thinh Nguyen <thinhn@xxxxxxxxxxxx>
---
drivers/usb/dwc3/core.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++++
drivers/usb/dwc3/core.h | 12 +++++++++++
2 files changed, 69 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 7d21f21707f5..56ca39b40a77 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -830,6 +830,41 @@ static int dwc3_core_init(struct dwc3 *dwc)
dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
}
+ /* Enable USB periodic ESS transmit and receive packet threshold */
+ if (dwc3_is_usb31(dwc) && dwc->dr_mode == USB_DR_MODE_HOST) {
+ if (dwc->rx_thr_sel_prd) {
+ u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
+ u8 rx_maxburst = dwc->rx_max_burst_prd;
+
+ reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
+ reg |= DWC3_USB31_RXTHRNUMPKTSEL_PRD;
+
+ reg &= ~DWC3_USB31_RXTHRNUMPKT_PRD(~0);
+ reg |= DWC3_USB31_RXTHRNUMPKT_PRD(rx_thr_num);
+
+ reg &= ~DWC3_USB31_MAXRXBURSTSIZE_PRD(~0);
+ reg |= DWC3_USB31_MAXRXBURSTSIZE_PRD(rx_maxburst);
+
+ dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
+ }
+
+ if (dwc->tx_thr_sel_prd) {
+ u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
+ u8 tx_maxburst = dwc->tx_max_burst_prd;
+
+ reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
+ reg |= DWC3_USB31_TXTHRNUMPKTSEL_PRD;
+
+ reg &= ~DWC3_USB31_TXTHRNUMPKT_PRD(~0);
+ reg |= DWC3_USB31_TXTHRNUMPKT_PRD(tx_thr_num);
+
+ reg &= ~DWC3_USB31_MAXTXBURSTSIZE_PRD(~0);
+ reg |= DWC3_USB31_MAXTXBURSTSIZE_PRD(tx_maxburst);
+
+ dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
+ }
+ }
+
return 0;
err4:
@@ -998,6 +1033,10 @@ static void dwc3_get_properties(struct dwc3 *dwc)
u8 lpm_nyet_threshold;
u8 tx_de_emphasis;
u8 hird_threshold;
+ u8 rx_thr_num_pkt_prd;
+ u8 rx_max_burst_prd;
+ u8 tx_thr_num_pkt_prd;
+ u8 tx_max_burst_prd;
/* default to highest possible threshold */
lpm_nyet_threshold = 0xff;
@@ -1032,6 +1071,18 @@ static void dwc3_get_properties(struct dwc3 *dwc)
&hird_threshold);
dwc->usb3_lpm_capable = device_property_read_bool(dev,
"snps,usb3_lpm_capable");
+ dwc->rx_thr_sel_prd = device_property_read_bool(dev,
+ "snps,rx_thr_sel_prd");
+ device_property_read_u8(dev, "snps,rx_thr_num_pkt_prd",
+ &rx_thr_num_pkt_prd);
+ device_property_read_u8(dev, "snps,rx_max_burst_prd",
+ &rx_max_burst_prd);
+ dwc->tx_thr_sel_prd = device_property_read_bool(dev,
+ "snps,tx_thr_sel_prd");
+ device_property_read_u8(dev, "snps,tx_thr_num_pkt_prd",
+ &tx_thr_num_pkt_prd);
+ device_property_read_u8(dev, "snps,tx_max_burst_prd",
+ &tx_max_burst_prd);
dwc->disable_scramble_quirk = device_property_read_bool(dev,
"snps,disable_scramble_quirk");
@@ -1079,6 +1130,12 @@ static void dwc3_get_properties(struct dwc3 *dwc)
dwc->hird_threshold = hird_threshold
| (dwc->is_utmi_l1_suspend << 4);
+ dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
+ dwc->rx_max_burst_prd = rx_max_burst_prd;
+
+ dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
+ dwc->tx_max_burst_prd = tx_max_burst_prd;
+
dwc->imod_interval = 0;
}
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index ce10954afe49..83a74d10fa82 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -835,6 +835,10 @@ struct dwc3_scratchpad_array {
* @test_mode_nr: test feature selector
* @lpm_nyet_threshold: LPM NYET response threshold
* @hird_threshold: HIRD threshold
+ * @rx_thr_num_pkt_prd: periodic ESS receive packet count
+ * @rx_max_burst_prd: max periodic ESS receive burst size
+ * @tx_thr_num_pkt_prd: periodic ESS transmit packet count
+ * @tx_max_burst_prd: max periodic ESS transmit burst size
* @hsphy_interface: "utmi" or "ulpi"
* @connected: true when we're connected to a host, false otherwise
* @delayed_status: true when gadget driver asks for delayed status
@@ -853,6 +857,8 @@ struct dwc3_scratchpad_array {
* @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
* @three_stage_setup: set if we perform a three phase setup
* @usb3_lpm_capable: set if hadrware supports Link Power Management
+ * @rx_thr_sel_prd: set to enable ESS receive packet threshold
+ * @tx_thr_sel_prd: set to enable ESS transmit packet threshold
* @disable_scramble_quirk: set if we enable the disable scramble quirk
* @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
* @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
@@ -995,6 +1001,10 @@ struct dwc3 {
u8 test_mode_nr;
u8 lpm_nyet_threshold;
u8 hird_threshold;
+ u8 rx_thr_num_pkt_prd;
+ u8 rx_max_burst_prd;
+ u8 tx_thr_num_pkt_prd;
+ u8 tx_max_burst_prd;
const char *hsphy_interface;
@@ -1012,6 +1022,8 @@ struct dwc3 {
unsigned setup_packet_pending:1;
unsigned three_stage_setup:1;
unsigned usb3_lpm_capable:1;
+ unsigned rx_thr_sel_prd:1;
+ unsigned tx_thr_sel_prd:1;
unsigned disable_scramble_quirk:1;
unsigned u2exit_lfps_quirk:1;
--
2.11.0
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