Hi, David Laight <David.Laight@xxxxxxxxxx> writes: >> > From: Felipe Balbi >> >> Sent: 07 April 2017 12:37 >> >> Just like we did for all other endpoint types, let's rely on a chained >> >> TRB pointing to ep0_bounce_addr in order to align transfer size. This >> >> will make the code simpler. >> > ... >> > >> > Is the dwc3 similar enough to xhci to have an 'immediate data' bit? >> > If so the aligning data could come from the 8 byte 'address' field. >> >> you mean like patch 1 in this very series? >> >> https://marc.info/?i=20170407113655.27569-1-felipe.balbi@xxxxxxxxxxxxxxx > > Not exactly, that seems to be using the trb memory itself as the buffer. > I'm guessing that can only work for 'read' TRB. > > If you look at the xhci docs (eg table 71 in section 6.4.1.2.1 of the rev 1.0 > copy I have) bit 6 of the last word is 'IDT'. > So 8 bytes of data are put into the bpl/bph fields - not a pointer at all. Right, it works similarly for DWC3 :-) However, instead of IDT we just set BPH/BPL to the address of the TRB itself. If I were to guess, it was made this way because peripheral controllers don't send SETUP packets, only receive them from a host. -- balbi
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