Re: Fwd: dwc2 and ping protocol

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Hi Nick,

In DMA mode handling NAKs internally by hardware performing starting from
core v2.71a. Before v2.71a handling NAKs should be performed by driver.
Your core is 2.65a.

Thanks,
Minas
 
On 3/11/2017 7:14 PM, Nick Hudson wrote:
> Hi,
>
> I'm using a mostly unmodified older version of the dwc2 driver in NetBSD
> taken from
>
>    git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
>
>
> Import latest dwc2 sources
>
> commit 192cb07f7928e8cb09a9851e6c0f7478baa3bc6d
> Author: John Youn <John.Youn@xxxxxxxxxxxx <mailto:John.Youn@xxxxxxxxxxxx>>
> Date:   Mon Jan 11 16:32:28 2016 -0800
>
>
> and it would appear that the hardware isn't handling the device NAKs in
> DMA mode. I understand from the code that in DMA mode the NAKs should be
> handled in hardware and not generate interrupts. Is this the case?
>
>
> Any pointers?
>
>
> Thanks,
> Nick
>
>
> dwctwo0: dwc2_hc_init()
> dwctwo0: DMA enabled
> dwctwo0: desc DMA disabled
> dwctwo0: set HCINTMSK to 00000006
> dwctwo0: set HAINTMSK to 00000080
> dwctwo0: set GINTMSK to f3000806
> dwctwo0: set HCCHAR(7) to 00881200
> dwctwo0: dwc2_hc_init: Channel 7
> dwctwo0:         Dev Addr: 2
> dwctwo0:         Ep Num: 2
> dwctwo0:         Is In: 0
> dwctwo0:         Is Low Speed: 0
> dwctwo0:         Ep Type: 2
> dwctwo0:         Max Pkt: 512
> dwctwo0: Queue non-periodic transactions
> dwctwo0:   NP Tx Req Queue Space Avail (before queue): 8
> dwctwo0:   NP Tx FIFO Space Avail (before queue): 912
> dwctwo0: dwc2_hc_start_transfer()
> dwctwo0: ping, DMA
> dwctwo0: no split
> dwctwo0: Wrote 80401000 to HCTSIZ(7)
> dwctwo0: dwc2_hc_start_transfer: Channel 7
> dwctwo0:         Xfer Size: 4096
> dwctwo0:         Num Pkts: 8
> dwctwo0:         Start PID: 0
> dwctwo0:         Multi Cnt: 1
> dwctwo0: Wrote 80981200 to HCCHAR(7)
> dwctwo0: --Host Channel Interrupt--, Channel 7
> dwctwo0:   hcint 0x00000012, hcintmsk 0x00000002, hcint&hcintmsk 0x00000002
> dwctwo0: --Host Channel 7 Interrupt: Channel Halted--
> dwctwo0: --Host Channel 7 Interrupt: DMA Channel Halted--
> dwctwo0: --Host Channel 7 Interrupt: NAK Received--
> dwctwo0: DWC_otg: dwc2_update_urb_state_abn: OUT, channel 7
> dwctwo0:   chan->start_pkt_count 8
> dwctwo0:   hctsiz.pktcnt 8
> dwctwo0:   chan->max_packet 512
> dwctwo0:   bytes_transferred 0
> dwctwo0:   urb->actual_length 0
> dwctwo0:   urb->transfer_buffer_length 4096
> dwctwo0: dwc2_halt_channel()
> dwctwo0: DMA enabled
> dwctwo0:   dwc2_release_channel: channel 7, halt_status 4
> dwctwo0: dwc2_deactivate_qh(0xffffffff8d046808,0xffffffff8cf6bce0,0)
> dwctwo0: dwc2_hcd_qh_deactivate()
> dwctwo0: dwc2_hcd_qh_unlink()
> dwctwo0: dwc2_hcd_qh_add()
> dwctwo0: dwc2_assign_and_init_hc(0xffffffff8d046808,0xffffffff8cf6bce0)
> dwctwo0: dwc2_hc_init()
> dwctwo0: DMA enabled
> dwctwo0: desc DMA disabled
> dwctwo0: set HCINTMSK to 00000006
> dwctwo0: set HAINTMSK to 00000001
> dwctwo0: set GINTMSK to f3000806
> dwctwo0: set HCCHAR(0) to 00881200
> dwctwo0: dwc2_hc_init: Channel 0
> dwctwo0:         Dev Addr: 2
> dwctwo0:         Ep Num: 2
> dwctwo0:         Is In: 0
> dwctwo0:         Is Low Speed: 0
> dwctwo0:         Ep Type: 2
> dwctwo0:         Max Pkt: 512
> dwctwo0: Queue non-periodic transactions
> dwctwo0:   NP Tx Req Queue Space Avail (before queue): 8
> dwctwo0:   NP Tx FIFO Space Avail (before queue): 912
> dwctwo0: dwc2_hc_start_transfer()
> dwctwo0: ping, DMA
> dwctwo0: no split
> dwctwo0: Wrote 80401000 to HCTSIZ(0)
> dwctwo0: dwc2_hc_start_transfer: Channel 0
> dwctwo0:         Xfer Size: 4096
> dwctwo0:         Num Pkts: 8
> dwctwo0:         Start PID: 0
> dwctwo0:         Multi Cnt: 1
> dwctwo0: Wrote 80981200 to HCCHAR(0)
> dwctwo0: --Host Channel Interrupt--, Channel 0
> dwctwo0:   hcint 0x00000012, hcintmsk 0x00000002, hcint&hcintmsk 0x00000002
> dwctwo0: --Host Channel 0 Interrupt: Channel Halted--
> dwctwo0: --Host Channel 0 Interrupt: DMA Channel Halted--
> dwctwo0: --Host Channel 0 Interrupt: NAK Received--
> dwctwo0: DWC_otg: dwc2_update_urb_state_abn: OUT, channel 0
> dwctwo0:   chan->start_pkt_count 8
> dwctwo0:   hctsiz.pktcnt 8
> dwctwo0:   chan->max_packet 512
> dwctwo0:   bytes_transferred 0
> dwctwo0:   urb->actual_length 0
> dwctwo0:   urb->transfer_buffer_length 4096
> dwctwo0: dwc2_halt_channel()
> dwctwo0: DMA enabled
> dwctwo0:   dwc2_release_channel: channel 0, halt_status 4
> dwctwo0: dwc2_deactivate_qh(0xffffffff8d046808,0xffffffff8cf6bce0,0)
> dwctwo0: dwc2_hcd_qh_deactivate()
> dwctwo0: dwc2_hcd_qh_unlink()
> dwctwo0: dwc2_hcd_qh_add()
> dwctwo0: dwc2_assign_and_init_hc(0xffffffff8d046808,0xffffffff8cf6bce0)
> dwctwo0: dwc2_hc_init()
>
>
>
>
>

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