Hi,
Lu Baolu <baolu.lu@xxxxxxxxxxxxxxx> writes:
> On 12/29/2016 07:00 PM, Felipe Balbi wrote:
>> Many other bits in USBSTS register are "clear-by-writing-1". Let's make
>> sure that we clear *only* STS_EINT and not any of the other bits as they
>> might be needed later.
>
> Bit 13~31 in status register is for RsvdP (Reserved and Preserved).
totally missed the "Preserved" part. Thanks
> This means these bits are reserved for future RW implementations.
> Software shall preserve the value read for writes.
>
> How about below helper?
>
> static inline void clear_status_rw1c_bit(u32 bit)
> {
> u32 status;
>
> status = readl(&xhci->op_regs->status);
> /* preserve RsvP bits and clear RO/RW1C/RsvZ bits */
> status &= ~0x1fff;
> status |= bit;
>
> writel(status, &xhci->op_regs->status);
> }
not sure, I have no problems with it, but it's for mathias to decide. If
anything, it should be prefixed by xhci_ so it's easier to use ftrace.
> Look into the code, I still find other two places where RW1C bits
> are not cleared correctly.
>
> In xhci_stop() and xhci_resume(), the RW1C bit is treated as a RW type.
>
> 724 temp = readl(&xhci->op_regs->status);
> 725 writel(temp & ~STS_EINT, &xhci->op_regs->status);
>
> I will correct these in a separated patch and cc stable as well.
That's cool. Then I can drop this patch from my series.
--
balbi
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