Hi,
Lu Baolu <baolu.lu@xxxxxxxxxxxxxxx> writes:
>> Commit 50c763f8c1bac ("usb: dwc3: Set the ClearPendIN bit on Clear
>> Stall EP command") sets ClearPendIN bit for all IN endpoints in
>> v2.60a+ cores no matter which speed mode they're in. This causes
>> Clear Stall EP command failing on some Intel devices.
>>
>> In page 539 of 2.60a specification, it says:
>>
>> "When issuing Clear Stall command for IN endpoints in SuperSpeed
>> mode, the software must set the "ClearPendIN" bit to '1' to
>> clear any pending IN transcations, so that the device does not
>> expect any ACK TP from the host for the data sent earlier."
>>
>> It's obviously that we only need to apply this rule to those IN
>> endpoints in SuperSpeed mode.
>>
>> Fixes: 50c763f8c1bac ("usb: dwc3: Set the ClearPendIN bit on Clear Stall EP command")
>> Cc: stable@xxxxxxxxxxxxxxx # 4.7+
>> Signed-off-by: Lu Baolu <baolu.lu@xxxxxxxxxxxxxxx>
>> ---
>> drivers/usb/dwc3/gadget.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
>> index 7a8d3d8..f1858d6 100644
>> --- a/drivers/usb/dwc3/gadget.c
>> +++ b/drivers/usb/dwc3/gadget.c
>> @@ -348,7 +348,8 @@ static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
>> * IN transfers due to a mishandled error condition. Synopsys
>> * STAR 9000614252.
>> */
>> - if (dep->direction && (dwc->revision >= DWC3_REVISION_260A))
>> + if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
>> + (dwc->maximum_speed >= USB_SPEED_SUPER))
>> cmd |= DWC3_DEPCMD_CLEARPENDIN;
>>
>> memset(¶ms, 0, sizeof(params));
>
> Oh, my bad.
>
> I'm sending you a patch which hasn't been verified on the real
> hardware yet.
>
> My mind goes blank after a whole day's work. Poor me. :-(
happens to all of us ;-)
> I will send you a refreshed one tomorrow. Really sorry about it.
no problem, thanks
--
balbi
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