This adds DT support for TI DA8xx/OMAP-L1x/AM17xx/AM18xx MUSB driver
Signed-off-by: Petr Kulhavy <petr@xxxxxxxxx>
---
drivers/usb/musb/da8xx.c | 88 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/drivers/usb/musb/da8xx.c b/drivers/usb/musb/da8xx.c
index b03d3b8..371fd74 100644
--- a/drivers/usb/musb/da8xx.c
+++ b/drivers/usb/musb/da8xx.c
@@ -6,6 +6,9 @@
* Based on the DaVinci "glue layer" code.
* Copyright (C) 2005-2006 by Texas Instruments
*
+ * DT support
+ * Copyright (c) 2016 Petr Kulhavy, Barix AG <petr@xxxxxxxxx>
+ *
* This file is part of the Inventra Controller Driver for Linux.
*
* The Inventra Controller Driver for Linux is free software; you
@@ -36,6 +39,7 @@
#include <mach/da8xx.h>
#include <linux/platform_data/usb-davinci.h>
+#include <linux/of_platform.h>
#include "musb_core.h"
@@ -134,6 +138,37 @@ static inline void phy_off(void)
__raw_writel(cfgchip2, CFGCHIP2);
}
+static inline int get_phy_refclk_cfg(struct device_node *np)
+{
+ u32 freq;
+
+ if (!of_property_read_u32(np, "ti,phy20-refclock-frequency", &freq))
+ return -EINVAL;
+
+ switch (freq) {
+ case 12000000:
+ return CFGCHIP2_REFFREQ_12MHZ;
+ case 13000000:
+ return CFGCHIP2_REFFREQ_13MHZ;
+ case 19200000:
+ return CFGCHIP2_REFFREQ_19_2MHZ;
+ case 20000000:
+ return CFGCHIP2_REFFREQ_20MHZ;
+ case 24000000:
+ return CFGCHIP2_REFFREQ_24MHZ;
+ case 26000000:
+ return CFGCHIP2_REFFREQ_26MHZ;
+ case 38400000:
+ return CFGCHIP2_REFFREQ_38_4MHZ;
+ case 40000000:
+ return CFGCHIP2_REFFREQ_40MHZ;
+ case 48000000:
+ return CFGCHIP2_REFFREQ_48MHZ;
+ default:
+ return -EINVAL;
+ }
+}
+
/*
* Because we don't set CTRL.UINT, it's "important" to:
* - not read/write INTRUSB/INTRUSBE (except during
@@ -482,6 +517,12 @@ static const struct platform_device_info da8xx_dev_info = {
.dma_mask = DMA_BIT_MASK(32),
};
+static const struct musb_hdrc_config da830_config = {
+ .ram_bits = 10,
+ .num_eps = 5,
+ .multipoint = 1,
+};
+
static int da8xx_probe(struct platform_device *pdev)
{
struct resource musb_resources[2];
@@ -490,6 +531,7 @@ static int da8xx_probe(struct platform_device *pdev)
struct da8xx_glue *glue;
struct platform_device_info pinfo;
struct clk *clk;
+ struct device_node *np = pdev->dev.of_node;
int ret = -ENOMEM;
@@ -515,6 +557,43 @@ static int da8xx_probe(struct platform_device *pdev)
glue->dev = &pdev->dev;
glue->clk = clk;
+ if (IS_ENABLED(CONFIG_OF) && np) {
+ int phy20_refclk_cfg;
+ u32 cfgchip2;
+
+ pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+ if (!pdata) {
+ ret = -ENOMEM;
+ goto err5;
+ }
+
+ pdata->config = &da830_config;
+ pdata->mode = musb_get_mode(&pdev->dev);
+ pdata->power = musb_get_power(&pdev->dev);
+
+ cfgchip2 = __raw_readl(CFGCHIP2);
+ cfgchip2 &= ~CFGCHIP2_USB2PHYCLKMUX;
+ /* optional parameter reference clock source
+ * true = use PLL, false = use external clock pin
+ */
+ if (of_property_read_bool(np, "ti,phy20-clkmux-pll"))
+ cfgchip2 |= CFGCHIP2_USB2PHYCLKMUX;
+ __raw_writel(cfgchip2, CFGCHIP2);
+
+ phy20_refclk_cfg = get_phy_refclk_cfg(np);
+ if (phy20_refclk_cfg < 0) {
+ dev_err(&pdev->dev,
+ "PHY 2.0 clock frequency invalid or undefined\n");
+ ret = -EINVAL;
+ goto err5;
+ }
+
+ cfgchip2 = __raw_readl(CFGCHIP2);
+ cfgchip2 &= ~CFGCHIP2_REFFREQ;
+ cfgchip2 |= phy20_refclk_cfg;
+ __raw_writel(cfgchip2, CFGCHIP2);
+ }
+
pdata->platform_ops = &da8xx_ops;
glue->phy = usb_phy_generic_register();
@@ -582,11 +661,20 @@ static int da8xx_remove(struct platform_device *pdev)
return 0;
}
+static const struct of_device_id da8xx_id_table[] = {
+ {
+ .compatible = "ti,da830-musb",
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, da8xx_id_table);
+
static struct platform_driver da8xx_driver = {
.probe = da8xx_probe,
.remove = da8xx_remove,
.driver = {
.name = "musb-da8xx",
+ .of_match_table = of_match_ptr(da8xx_id_table),
},
};
--
1.9.1
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