Hello.
On 01/29/2016 07:18 PM, Krzysztof Hałasa wrote:
The unclear part here is for IXP4xx, which supports both big-endian
and little-endian configurations. So far, the driver has done
no byteswap in either case. I suspect that is wrong and it would
actually need to swap in one or the other case, but I don't know
which.
If at all, I guess it should swap in LE mode. But it's far from certain.
It's also possible that there is some magic setting in
the chip that makes the endianess of the MMIO register match the
CPU, and in that case, the code actually does the right thing
for all configurations, both before and after this patch.
This is IMHO most probable.
Actually, the IXP4xx is "natural" in BE mode (except for PCI) and
normally in LE mode it's order-coherent, meaning 32-bit "integer"
accesses need no swapping, but 8-bit and (mostly unused) 16-bit
transfers need swapping.
Anyway, I think readl()/writel() do the right thing: in BE mode they
swap PCI accesses and don't swap normal registers,
Alas, readl()/writel() don't know what registers you are calling them for,
they were designed for PCI which is little-endian, so they will swap in BE mode.
MBR, Sergei
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