On 12/1/2015 2:34 PM, Florian Fainelli wrote:
On 25/10/15 15:52, Hauke Mehrtens wrote:
On 10/24/2015 12:40 AM, Florian Fainelli wrote:
On 23/10/15 14:37, Hauke Mehrtens wrote:
From: Rafał Miłecki <zajec5@xxxxxxxxx>
Signed-off-by: Rafał Miłecki <zajec5@xxxxxxxxx>
Signed-off-by: Hauke Mehrtens <hauke@xxxxxxxxxx>
---
[snip]
+
+ switch (chipinfo->id) {
+ case BCMA_CHIP_ID_BCM4707:
All the code above cries for being a proper USB PHY driver, is there a
particular reason why it needs to be living in bcma-hcd.c other than
being convenient?
No, there isn't.
I will try to create a usb phy driver and connect it with bcma-hcd.c. Is
there already a phy driver which does this stuff? I think this PHY is
shared with the 3rd PCIe controller on some SoCs.
Meant to reply to this earlier, I would look at
drivers/phy/phy-bcm-cygnus-pcie.c which may help here.
Ah, not really. The current Cygnus PCIe PHY driver does nothing more
than reading/writing to some iproc registers that directly control the
PCIe Serdes in Cygnus. It does not deal with reading/writing to the
internal PHY registers through the MII bus.
+ if (chipinfo->rev == 4) {
+ /* For NS-B0, USB3 PLL Block */
+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
+ iowrite32(0x587e8000, ccb->mii + 0x004);
+
+ /* Clear ana_pllSeqStart */
+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
+ iowrite32(0x58061000, ccb->mii + 0x004);
---
Florian
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