Hi Felipe, > > With 1.94a and newer, DWC3_GUSB3PIPECTL(0) and DWC3_GUSB2PHYCFG(0) > > keep their ctx over any kind of soft reset. And any configurations > > done to them here will take affect the latest when > > dwc3_core_soft_reset() is called. > > /me goes read Databook again. > > You're right. You're using the soft reset bit from DCTL, that only > resets the device side, not any global register. There are two details > which you don't appear to take care of, however. > > According to Table 7-82 on Databook 2.93a (page 725), bit 30 CSFTRST, > it's said that "Once this bit is cleared, the software must wait at > least 3 PHY clocks before accessing the PHY domain". Ok, I'll add a delay for that. > Futher down is > states that "Once a new clock is selected, the PHY domain must be reset > for proper operation". All PHYs will be reset once we call dwc3_core_soft_reset() and we do not need them to be operational before that, except in case of ULPI in order to register the interface. To make sure the ULPI interface and PHY are operational we call dwc3_soft_reset() which does everything needed for us. When we use DCTL.SoftRst the core will reset also the ULPI PHY (PHYSoftRst in DWC3_GUSB2PHYCFG(0) has no effect with ULPI). So dwc3_phy_setup() configures the PHY interfaces but it does not initialize them or the PHYs. dwc3_core_soft_reset() continues to take care of that in any case, so there is no reason to duplicate it. I think we need to point this out in the description comment of dwc3_phy_setup(). Thanks, -- heikki -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
