On Fri, 10 Oct 2014, Kevin Cernekee wrote:
> OHCI_QUIRK_FRAME_NO is currently set under either of the following
> conditions:
>
> 1) If a ppc-of-ohci DT node indicates a compatible string of
> "fsl,mpc5200-ohci" or "mpc5200-ohci"
>
> 2) If usb_ohci_pdata->no_big_frame_no is set
>
> For #1, the affected platforms already enable CONFIG_PPC_MPC52xx.
> For #2, there are currently no in-tree users.
>
> So we can safely remove the #ifdef, and thereby allow OHCI_QUIRK_FRAME_NO
> to be used by other (non-PPC) platforms that have the same property.
> bcm63xx and bcm3384 are two such users.
Sorry, but I can't understand this patch description. What #ifdef does
it refer to?
By comparing the description with the patch, it looks like you _wanted_
to say something along these lines:
The bcm63xx and bcm3384 platforms need to set
OHCI_QUIRK_FRAME_NO, but they are non-PPC platforms and
don't enable CONFIG_PPC_MPC52xx. Therefore this patch changes
the code that uses OHCI_QUIRK_FRAME_NO, making it not depend
on CONFIG_PPC_MPC52xx.
Does that properly describe what you are doing?
Alan Stern
> Signed-off-by: Kevin Cernekee <cernekee@xxxxxxxxx>
> ---
> drivers/usb/host/ohci.h | 19 +++++++++----------
> 1 file changed, 9 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h
> index 59f4245..bc46228 100644
> --- a/drivers/usb/host/ohci.h
> +++ b/drivers/usb/host/ohci.h
> @@ -647,23 +647,22 @@ static inline u32 hc32_to_cpup (const struct ohci_hcd *ohci, const __hc32 *x)
>
> /*-------------------------------------------------------------------------*/
>
> -/* HCCA frame number is 16 bits, but is accessed as 32 bits since not all
> - * hardware handles 16 bit reads. That creates a different confusion on
> - * some big-endian SOC implementations. Same thing happens with PSW access.
> +/*
> + * The HCCA frame number is 16 bits, but is accessed as 32 bits since not all
> + * hardware handles 16 bit reads. Depending on the SoC implementation, the
> + * frame number can wind up in either bits [31:16] (default) or
> + * [15:0] (OHCI_QUIRK_FRAME_NO) on big endian hosts.
> + *
> + * Somewhat similarly, the 16-bit PSW fields in a transfer descriptor are
> + * reordered on BE.
> */
>
> -#ifdef CONFIG_PPC_MPC52xx
> -#define big_endian_frame_no_quirk(ohci) (ohci->flags & OHCI_QUIRK_FRAME_NO)
> -#else
> -#define big_endian_frame_no_quirk(ohci) 0
> -#endif
> -
> static inline u16 ohci_frame_no(const struct ohci_hcd *ohci)
> {
> u32 tmp;
> if (big_endian_desc(ohci)) {
> tmp = be32_to_cpup((__force __be32 *)&ohci->hcca->frame_no);
> - if (!big_endian_frame_no_quirk(ohci))
> + if (!(ohci->flags & OHCI_QUIRK_FRAME_NO))
> tmp >>= 16;
> } else
> tmp = le32_to_cpup((__force __le32 *)&ohci->hcca->frame_no);
>
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