On 5/31/2014 5:35 AM, Paul Zimmerman wrote:
From: Felipe Balbi [mailto:balbi@xxxxxx]
Sent: Friday, May 30, 2014 4:42 PM
On Fri, May 23, 2014 at 11:39:24AM -0700, Paul Zimmerman wrote:
Newer DWC3 controllers can be built for USB 2.0-only mode, where
most of the USB 3.0 circuitry is left out. To support this mode,
the driver must limit the speed programmed into the DCFG register
to Hi-Speed or lower.
Reads and writes to the PIPECTL register are left as-is, since
they should be no-ops in USB 2.0-only mode. Calls to phy_init()
etc. for the USB3 phy are also left as-is, since the no-op USB3
phy should be used for USB 2.0-only mode controllers.
Signed-off-by: Paul Zimmerman <paulz@xxxxxxxxxxxx>
---
Hi Felipe,
Does this look OK to you? I think it is fine to leave the PIPECTL
accesses and the phy_init() calls as-is, but if you would prefer
that I also conditionalize those I can do that. We have at least
one customer who will need this feature fairly soon, so we would
like to get this in without too much delay, although I guess we
missed the 3.16 merge window.
I like this a lot :-) Very nice of Synopsys to support this
configuration. Could you just let me know which versions of the core
support this configuration ? We have AM437x which has this sort of
"quirk" although, I think it's done using a TI-specific "modification",
perhaps ?
AM437x is version 2.40a
It has been officially supported since 2.60a. But it's possible that
customers have hacked up something like this on their own with previous
versions, so the exact version number might not mean much. The patch
should work for all versions of the core, because the
DWC_USB3_SSPHY_INTERFACE bits have always been there, going back to
preproduction versions of the core.
It has been pointed out to me that DT can already be used to limit the
max speed, using the 'maximum-speed' property (duh). But I think we
still want the patch for non-DT platforms like dwc3-pci.
In TI implementation (AM437x)
DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) is read as 1.
--
-George
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