On Tue, Apr 15, 2014 at 04:06:11PM +0200, Johan Hovold wrote:
> On Mon, Apr 14, 2014 at 07:54:17PM +0000, Karl Palsson wrote:
> > + if (C_PARENB(tty)) {
> > + if (C_PARODD(tty)) {
> > + if (C_CMSPAR(tty)) {
>
> Thanks for fixing the C_CMSPAR macro, but you didn't address my other
> comments on v1.
>
> > + dev_dbg(&port->dev, "parity = mark\n");
> > + par_flags = 0xeb;
> > + } else {
> > + dev_dbg(&port->dev, "parity = odd\n");
> > + par_flags = 0xcb;
> > + }
> > + } else {
> > + if (C_CMSPAR(tty)) {
> > + dev_dbg(&port->dev, "parity = space\n");
> > + par_flags = 0xfb;
> > + } else {
> > + dev_dbg(&port->dev, "parity = even\n");
> > + par_flags = 0xdb;
> > + }
> > + }
> > + } else {
> > + dev_dbg(&port->dev, "parity = none\n");
> > + par_flags = 0xc3;
> > + }
> > + ch341_control_out(port->serial->dev, 0x9a, 0x2518, par_flags);
>
> Specifically, I asked if you are able to make sense of the values of
> register 0x2518. The reason I ask is that your patch changes the value
> of that register from 0x50 (set in ch341_configure) to 0xc3 (when no
> parity is used) and I want to make sure that you're not inadvertently
> changing some other setting.
>
> Do you know what those other bits do? Do they encode the number of data
> and stop bits?
>
> From a quick glance it seems like
>
> 0xc0 parity mode (2 bits)
> 0x08 parity enable
>
> but your patch now also sets bits 0x83 and clears bit 0x10.
That should have been:
0x30 parity mode (2 bits)
0x08 parity enable
and your patch now always sets bits 0x83.
Johan
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