From: Sarah Sharp
> On Wed, Jan 29, 2014 at 12:50:04PM +0200, Xenia Ragiadakou wrote:
> >
> > Like Bjørn already pointed out, I think too the problem is that the
> > USB3.0 host controller does not support 64 bit addressing (this can
> > be seen from the first bit of HCC PARAMS that is 0) but the patch
> > does not take it into account and blindly tries to perform 64bit
> > write accesses just because your system is 64bit. My mistake. I will
> > try to find a solution for that and send a patch when I ll return
> > home.
>
> I think the solution should be to just revert the writeq patch, and
> leave the xhci_write64 in place. We can always optimize that function
> later to do a writeq if the host supports 64-bit writes, but we'll have
> to analyze whether the performance impact of doing so makes sense.
The two 32bit writes will be seen by the PCIe system as writes
to the same address - which will force it to synchronise them.
This may well mean that the second can't be sent until the
first completes.
OTOH the only 64bit writes are during setup and error paths.
In particular the doorbell writes are 32bit.
So the additional cost (equivalent to a PCIe read) probably
doesn't really matter at all.
David
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