On Fri, Jan 17, 2014 at 04:52:30PM +0100, Matthieu CASTET wrote:
> ENDPTFLUSH and ENDPTPRIME registers are set by software and clear
> by hardware. There is a bit for each endpoint. When we are setting
> a bit for an endpoint we should make sure we do not touch other
> endpoint bit. There is a race condition if the hardware clear the
> bit between the read and the write in hw_write.
>
> Signed-off-by: Matthieu CASTET <matthieu.castet@xxxxxxxxxx>
> Tested-by: Michael Grzeschik <mgrzeschik@xxxxxxxxxxxxxx>
> ---
> drivers/usb/chipidea/udc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
> index 69d20fb..9e2e39b 100644
> --- a/drivers/usb/chipidea/udc.c
> +++ b/drivers/usb/chipidea/udc.c
> @@ -105,7 +105,7 @@ static int hw_ep_flush(struct ci_hdrc *ci, int num, int dir)
>
> do {
> /* flush any pending transfer */
> - hw_write(ci, OP_ENDPTFLUSH, BIT(n), BIT(n));
> + hw_write(ci, OP_ENDPTFLUSH, ~0, BIT(n));
> while (hw_read(ci, OP_ENDPTFLUSH, BIT(n)))
> cpu_relax();
> } while (hw_read(ci, OP_ENDPTSTAT, BIT(n)));
> @@ -205,7 +205,7 @@ static int hw_ep_prime(struct ci_hdrc *ci, int num, int dir, int is_ctrl)
> if (is_ctrl && dir == RX && hw_read(ci, OP_ENDPTSETUPSTAT, BIT(num)))
> return -EAGAIN;
>
> - hw_write(ci, OP_ENDPTPRIME, BIT(n), BIT(n));
> + hw_write(ci, OP_ENDPTPRIME, ~0, BIT(n));
>
> while (hw_read(ci, OP_ENDPTPRIME, BIT(n)))
> cpu_relax();
> --
> 1.8.5.2
>
>
>
Applied, thanks.
--
Best Regards,
Peter Chen
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