Hi,
ENDPTFLUSH and ENDPTPRIME are registers that are set by software and
clear by hardware.
The current code manipulate them with
"hw_write(ci, register, BIT(n), BIT(n));"
This do not look sane to me, because hw_write will read the register,
apply the mask and write the value.
What happen if the hardware clear the value of another endpoint between
the read and the write ?
I think we don't see any problem ATM because the endpoint operation
are serialized.
Do you thing a patch like this is ok ?
Matthieu
diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
index 69d20fb..9e2e39b 100644
--- a/drivers/usb/chipidea/udc.c
+++ b/drivers/usb/chipidea/udc.c
@@ -105,7 +105,7 @@ static int hw_ep_flush(struct ci_hdrc *ci, int num,
int dir)
do {
/* flush any pending transfer */
- hw_write(ci, OP_ENDPTFLUSH, BIT(n), BIT(n));
+ hw_write(ci, OP_ENDPTFLUSH, ~0, BIT(n));
while (hw_read(ci, OP_ENDPTFLUSH, BIT(n)))
cpu_relax();
} while (hw_read(ci, OP_ENDPTSTAT, BIT(n)));
@@ -205,7 +205,7 @@ static int hw_ep_prime(struct ci_hdrc *ci, int num,
int dir, int is_ctrl) if (is_ctrl && dir == RX && hw_read(ci,
OP_ENDPTSETUPSTAT, BIT(num))) return -EAGAIN;
- hw_write(ci, OP_ENDPTPRIME, BIT(n), BIT(n));
+ hw_write(ci, OP_ENDPTPRIME, ~0, BIT(n));
while (hw_read(ci, OP_ENDPTPRIME, BIT(n)))
cpu_relax();
--
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