Re: [boot crash] Re: [tip:x86/mce3] x86, mce: use 64bit machine check code on 32bit
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- Subject: Re: [boot crash] Re: [tip:x86/mce3] x86, mce: use 64bit machine check code on 32bit
- From: Ingo Molnar <mingo@xxxxxxx>
- Date: Mon, 17 Aug 2009 13:00:35 +0200
- Cc: Hidetoshi Seto <seto.hidetoshi@xxxxxxxxxxxxxx>, linux-kernel@xxxxxxxxxxxxxxx, mingo@xxxxxxxxxx, hpa@xxxxxxxxx, tglx@xxxxxxxxxxxxx, Yinghai Lu <yinghai@xxxxxxxxxx>, Huang Ying <ying.huang@xxxxxxxxx>, "Rafael J. Wysocki" <rjw@xxxxxxx>, linux-tip-commits@xxxxxxxxxxxxxxx
- In-reply-to: <4A893746.4040402@xxxxxxxxxxxxxxx>
- References: <tip-4efc0670baf4b14bc95502e54a83ccf639146125@xxxxxxxxxxxxxx> <20090812113652.GA19632@xxxxxxx> <4A88E3E4.40506@xxxxxxxxxxxxxx> <20090817083544.GC15390@xxxxxxx> <4A891E17.1090901@xxxxxxxxxxxxxx> <4A893746.4040402@xxxxxxxxxxxxxxx>
- User-agent: Mutt/1.5.18 (2008-05-17)
* Andi Kleen <ak@xxxxxxxxxxxxxxx> wrote:
> Hidetoshi Seto wrote:
>
>> One possibility is: if the BIOS doesn't clear status in banks,
>> new mce codes will try to log such junks.
>>
>> If the junk is totally junk but can be decoded as a valid log
>> with MISCV or ADDRV bit, and if the cpu try to access register
>> which is not implemented (e.g. IA32_MCi_MISC/ADDR), then such
>> access might cause a general protection exception. (ref. ASDM 3A
>> 15.3.2.3)
>
> The MCA declares if it comes with ADDR or MISC in a status bit and
> the MCA code only accesses these MSRs if these status bits are
> set. Also I believe P3 implemented ADDR at least, likely even
> MISC.
>
> The old 32bit MCA code did that too
That's true, but did you also want to make a specific point?
Ingo
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