Hidetoshi Seto wrote:
One possibility is: if the BIOS doesn't clear status in banks, new mce codes will try to log such junks. If the junk is totally junk but can be decoded as a valid log with MISCV or ADDRV bit, and if the cpu try to access register which is not implemented (e.g. IA32_MCi_MISC/ADDR), then such access might cause a general protection exception. (ref. ASDM 3A 15.3.2.3)
The MCA declares if it comes with ADDR or MISC in a status bit and the MCA code only accesses these MSRs if these status bits are set. Also I believe P3 implemented ADDR at least, likely even MISC. The old 32bit MCA code did that too -Andi -- To unsubscribe from this list: send the line "unsubscribe linux-tip-commits" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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