DFLL is a dedicated clock source for the Fast CPU. The DFLL is based on a ring oscillator and translates voltage changes into frequency compensation changes needed to prevent the CPU from failing and is essential for correct CPU frequency scaling. Svyatoslav Ryhel (3): drivers: cpufreq: add Tegra 4 support drivers: clk: tegra: add DFLL support for Tegra 4 ARM: tegra: Add DFLL clock support on Tegra 4 arch/arm/boot/dts/nvidia/tegra114.dtsi | 34 +++++++ drivers/clk/tegra/Kconfig | 2 +- drivers/clk/tegra/clk-tegra114.c | 30 +++++- drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 104 +++++++++++++++++++++ drivers/clk/tegra/clk.h | 2 - drivers/cpufreq/cpufreq-dt-platdev.c | 1 + drivers/cpufreq/tegra124-cpufreq.c | 5 +- include/dt-bindings/reset/tegra114-car.h | 13 +++ 8 files changed, 182 insertions(+), 9 deletions(-) create mode 100644 include/dt-bindings/reset/tegra114-car.h -- 2.43.0
