On 9/26/2024 4:45 AM, Russell King (Oracle) wrote:
> On Wed, Sep 25, 2024 at 04:01:28PM -0700, Abhishek Chauhan wrote:
>> diff --git a/drivers/net/phy/aquantia/aquantia_main.c b/drivers/net/phy/aquantia/aquantia_main.c
>> index e982e9ce44a5..88ba12aaf6e0 100644
>> --- a/drivers/net/phy/aquantia/aquantia_main.c
>> +++ b/drivers/net/phy/aquantia/aquantia_main.c
>> @@ -767,6 +767,33 @@ static int aqr111_config_init(struct phy_device *phydev)
>> return aqr107_config_init(phydev);
>> }
>>
>> +static int aqr115c_get_features(struct phy_device *phydev)
>> +{
>> + int ret;
>> + __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
>
> Networking uses reverse-christmas tree ordering for variables. Please
> swap the order of these.
>
> Also, I think this would be better:
>
> unsigned long *supported = phydev->supported;
>
> You don't actually need a separate mask.
>
>> +
>> + /* Normal feature discovery */
>> + ret = genphy_c45_pma_read_abilities(phydev);
>> + if (ret)
>> + return ret;
>> +
>> + /* PHY FIXUP */
>> + /* Although the PHY sets bit 12.18.19.48, it does not support 5G/10G modes */
>> + linkmode_clear_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, phydev->supported);
>> + linkmode_clear_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, phydev->supported);
>> + linkmode_clear_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, phydev->supported);
>> + linkmode_clear_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, phydev->supported);
>
> For the above four, s/phydev->supported/supported/
>
>> +
>> + /* Phy supports Speeds up to 2.5G with Autoneg though the phy PMA says otherwise */
>> + linkmode_copy(supported, phy_gbit_features);
>> + linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT, supported);
>> + linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, supported);
>> +
>> + linkmode_or(phydev->supported, supported, phydev->supported);
>
> Drop this linkmode_or().
>
> You'll then be modifying phydev->supported directly, which is totally
> fine.
Noted!.
Thanks Russell. Appreciate all the reviews.
>
