> -----Original Message-----
> From: Mark Brown <broonie@xxxxxxxxxx>
> Sent: 24 February 2023 22:17
> To: Krishna Yarlagadda <kyarlagadda@xxxxxxxxxx>
> Cc: linux-spi@xxxxxxxxxxxxxxx; linux-tegra@xxxxxxxxxxxxxxx; linux-
> kernel@xxxxxxxxxxxxxxx; thierry.reding@xxxxxxxxx; Jonathan Hunter
> <jonathanh@xxxxxxxxxx>; Sowjanya Komatineni
> <skomatineni@xxxxxxxxxx>; Laxman Dewangan <ldewangan@xxxxxxxxxx>
> Subject: Re: [PATCH] spi: tegra210-quad: Fix iterator outside loop
>
> On Fri, Feb 24, 2023 at 10:05:13PM +0530, Krishna Yarlagadda wrote:
>
> > msg->actual_length += xfer->len;
> > + if (!xfer->cs_change && transfer_phase == DATA_TRANSFER)
> {
> > + tegra_qspi_transfer_end(spi);
> > + spi_transfer_delay_exec(xfer);
> > + }
> > transfer_phase++;
> > }
> > - if (!xfer->cs_change) {
> > - tegra_qspi_transfer_end(spi);
> > - spi_transfer_delay_exec(xfer);
> > - }
>
> This looks like it'll do the wrong thing and do a change on every
> transfer if cs_change isn't set?
This condition is hit only in data phase which is end of message.
KY
