On 29/06/2022 08:04, Vidya Sagar wrote: > Add support for PCIe controllers that operate in the endpoint mode > in tegra234 chipset. > > Signed-off-by: Vidya Sagar <vidyas@xxxxxxxxxx> > --- > V3: > * New patch in this series > > .../bindings/pci/nvidia,tegra194-pcie-ep.yaml | 141 +++++++++++++++++- > 1 file changed, 136 insertions(+), 5 deletions(-) > All comments from patch #3 apply. > diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml > index 4f7cb7fe378e..11778eb92c47 100644 > --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml > +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml > @@ -17,6 +17,7 @@ description: | > in they can work either in root port mode or endpoint mode but one at a time. > > On Tegra194, controllers C0, C4 and C5 support endpoint mode. > + On Tegra234, controllers C5, C6, C7 and C10 support endpoint mode. > > Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to operate in the > endpoint mode because of the way the platform is designed. > @@ -25,6 +26,7 @@ properties: > compatible: > enum: > - nvidia,tegra194-pcie-ep > + - nvidia,tegra234-pcie-ep > > reg: (...) > + - if: > + properties: > + compatible: > + contains: > + enum: > + - nvidia,tegra234-pcie > + then: > + properties: > + nvidia,bpmp: > + items: > + - items: > + - minimum: 0 > + maximum: 0xffffffff > + - enum: [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 ] > + > unevaluatedProperties: false > > required: > @@ -174,6 +245,7 @@ required: > - power-domains > - reset-gpios > - num-lanes > + - vddio-pex-ctl-supply This is unexpected and looks unrelated. Best regards, Krzysztof
