On 23-06-22, 22:15, Jon Hunter wrote:
> On 26/05/2022 12:42, Viresh Kumar wrote:
> > diff --git a/drivers/soc/tegra/common.c b/drivers/soc/tegra/common.c
> > index 32c346b72635..49a5360f4507 100644
> > --- a/drivers/soc/tegra/common.c
> > +++ b/drivers/soc/tegra/common.c
> > @@ -108,12 +108,6 @@ int devm_tegra_core_dev_init_opp_table(struct device *dev,
> > u32 hw_version;
> > int err;
> > - err = devm_pm_opp_set_clkname(dev, NULL);
> > - if (err) {
> > - dev_err(dev, "failed to set OPP clk: %d\n", err);
> > - return err;
> > - }
> > -
> > /* Tegra114+ doesn't support OPP yet */
> > if (!of_machine_is_compatible("nvidia,tegra20") &&
> > !of_machine_is_compatible("nvidia,tegra30"))
>
>
> This appears to be breaking a few Tegra drivers. For example, on Tegra210
> Jetson TX1 I am seeing the following and the eMMC is no longer working ...
>
> [ 0.526729] sdhci-tegra 700b0600.mmc: dev_pm_opp_set_rate: device's opp table doesn't exist
> [ 0.526733] sdhci-tegra 700b0600.mmc: failed to set clk rate to 400000Hz: -19
> [ 0.528830] sdhci-tegra 700b0600.mmc: dev_pm_opp_set_rate: device's opp table doesn't exist
> [ 0.528833] sdhci-tegra 700b0600.mmc: failed to set clk rate to 400000Hz: -19
>
> I have seen another instance of this on Jetson Xavier NX ...
>
> [ 12.301336] tegra-pwm 32d0000.pwm: dev_pm_opp_set_rate: device's opp table doesn't exist
> [ 12.301350] tegra-pwm 32d0000.pwm: Failed to set max frequency: -19
>
> Bisect is point to this commit and so something is not working as
> expected.
Thanks again Jon.
This is what happens when the special code doesn't have a comment
attached with it. Neither the reviewer, nor the author remember why
the special piece was required :)
I had to go through the whole sequence, along with DT to understand
what might have broken this stuff :)
I will drop this patch and add this comment in its place:
diff --git a/drivers/soc/tegra/common.c b/drivers/soc/tegra/common.c
index 32c346b72635..9f3fdeb1a11c 100644
--- a/drivers/soc/tegra/common.c
+++ b/drivers/soc/tegra/common.c
@@ -108,6 +108,13 @@ int devm_tegra_core_dev_init_opp_table(struct device *dev,
u32 hw_version;
int err;
+ /*
+ * For some devices we don't have any OPP table in the DT, and in order
+ * to use the same code path for all the devices, we create a dummy OPP
+ * table for them via this call. The dummy OPP table is only capable of
+ * doing clk_set_rate() on invocation of dev_pm_opp_set_rate() and
+ * doesn't provide any other functionality.
+ */
err = devm_pm_opp_set_clkname(dev, NULL);
if (err) {
dev_err(dev, "failed to set OPP clk: %d\n", err);
Though there will still be a problem here with my changes, we don't
accept NULL clkname anymore for the set-clkname API. And tegra does
this to pick the first clock available in DT (at index 0) I think.
Other drivers (mostly qcom) who need such dummy OPP table, provide a
real clock name instead. Will it be possible to pass that here somehow
?
--
viresh
