Hi Viresh,
On 26/05/2022 12:42, Viresh Kumar wrote:
The OPP core already performs devm_pm_opp_set_clkname() with name as
NULL, the callers shouldn't be doing the same unless they have a
different clock name to add here.
Drop the call.
Cc: Dmitry Osipenko <digetx@xxxxxxxxx>
Signed-off-by: Viresh Kumar <viresh.kumar@xxxxxxxxxx>
---
drivers/soc/tegra/common.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/drivers/soc/tegra/common.c b/drivers/soc/tegra/common.c
index 32c346b72635..49a5360f4507 100644
--- a/drivers/soc/tegra/common.c
+++ b/drivers/soc/tegra/common.c
@@ -108,12 +108,6 @@ int devm_tegra_core_dev_init_opp_table(struct device *dev,
u32 hw_version;
int err;
- err = devm_pm_opp_set_clkname(dev, NULL);
- if (err) {
- dev_err(dev, "failed to set OPP clk: %d\n", err);
- return err;
- }
-
/* Tegra114+ doesn't support OPP yet */
if (!of_machine_is_compatible("nvidia,tegra20") &&
!of_machine_is_compatible("nvidia,tegra30"))
This appears to be breaking a few Tegra drivers. For example, on Tegra210
Jetson TX1 I am seeing the following and the eMMC is no longer working ...
[ 0.526729] sdhci-tegra 700b0600.mmc: dev_pm_opp_set_rate: device's opp table doesn't exist
[ 0.526733] sdhci-tegra 700b0600.mmc: failed to set clk rate to 400000Hz: -19
[ 0.528830] sdhci-tegra 700b0600.mmc: dev_pm_opp_set_rate: device's opp table doesn't exist
[ 0.528833] sdhci-tegra 700b0600.mmc: failed to set clk rate to 400000Hz: -19
I have seen another instance of this on Jetson Xavier NX ...
[ 12.301336] tegra-pwm 32d0000.pwm: dev_pm_opp_set_rate: device's opp table doesn't exist
[ 12.301350] tegra-pwm 32d0000.pwm: Failed to set max frequency: -19
Bisect is point to this commit and so something is not working as
expected.
Cheers
Jon
--
nvpublic
