On 2022-05-11 02:29, Besar Wicaksono wrote:
-----Original Message-----
From: Sudeep Holla <sudeep.holla@xxxxxxx>
Sent: Tuesday, May 10, 2022 1:40 PM
To: Besar Wicaksono <bwicaksono@xxxxxxxxxx>
Cc: Suzuki K Poulose <suzuki.poulose@xxxxxxx>; Will Deacon
<will@xxxxxxxxxx>; Sudeep Holla <sudeep.holla@xxxxxxx>;
catalin.marinas@xxxxxxx; mark.rutland@xxxxxxx; linux-arm-
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Michael.Williams@xxxxxxx; Thierry Reding <treding@xxxxxxxxxx>; Jonathan
Hunter <jonathanh@xxxxxxxxxx>; Vikram Sethi <vsethi@xxxxxxxxxx>;
Mathieu Poirier <mathieu.poirier@xxxxxxxxxx>
Subject: Re: [PATCH 0/2] perf: ARM CoreSight PMU support
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On Tue, May 10, 2022 at 12:13:19PM +0100, Will Deacon wrote:
On Tue, May 10, 2022 at 12:07:42PM +0100, Sudeep Holla wrote:
On Mon, May 09, 2022 at 11:02:23AM +0100, Suzuki K Poulose wrote:
Cc: Mike Williams, Mathieu Poirier
On 09/05/2022 10:28, Will Deacon wrote:
On Sun, May 08, 2022 at 07:28:08PM -0500, Besar Wicaksono wrote:
arch/arm64/configs/defconfig | 1 +
drivers/perf/Kconfig | 2 +
drivers/perf/Makefile | 1 +
drivers/perf/coresight_pmu/Kconfig | 10 +
drivers/perf/coresight_pmu/Makefile | 7 +
.../perf/coresight_pmu/arm_coresight_pmu.c | 1317
+++++++++++++++++
.../perf/coresight_pmu/arm_coresight_pmu.h | 147 ++
.../coresight_pmu/arm_coresight_pmu_nvidia.c | 300 ++++
.../coresight_pmu/arm_coresight_pmu_nvidia.h | 17 +
9 files changed, 1802 insertions(+)
How does this interact with all the stuff we have under
drivers/hwtracing/coresight/?
Absolutely zero, except for the name. The standard
is named "CoreSight PMU" which is a bit unfortunate,
given the only link, AFAIU, with the "CoreSight" architecture
is the Lock Access Register(LAR). For reference, the
drivers/hwtracing/coresight/ is purely "CoreSight" self-hosted
tracing and the PMU is called "cs_etm" (expands to coresight etm).
Otherwise the standard doesn't have anything to do with what
exists already in the kernel.
That's... a poor naming choice! But good, if it's entirely separate then I
don't have to worry about that. Just wanted to make sure we're not going
to
get tangled up in things like ROM tables and Coresight power domains for
these things.
OK, now that triggered another question/thought.
1. Do you need to do active power management for these PMUs ? Or like
CPU PMUs, do you reject entering low power states if there is active
session in progress. If there is active session, runtime PM won't get
triggered but if there is system wide suspend, how is that dealt with ?
Looking at the other uncore/system PMUs, none of the drivers support PM ops.
NVIDIA system PMU also does not get power gated and system suspend is not
supported. But just like other uncore PMU driver, this driver supports CPU hotplug.
If PM is needed, the required info should have been expressed in ACPI.
2. Assuming you need some sort of PM, and since this is static table(which
I really don't like/prefer but it is out there 🙁), how do you plan to
get the power domain related information.
I guess the APMT spec in section 2.2 may cover this. If a PMU implementation has
properties beyond what is defined in the spec, these properties can be described in DSDT.
The driver doesn’t take care of this currently, so this is a room for future improvement.
Yes, I assume it's essentially the same story as for MPAM MSCs in this
respect. Plus it means that MSI support will be similarly fun, where
we'll need to have a corresponding DSDT device via which we can request
the interrupt, because that needs to further correlate to an IORT Named
Component node describing the ITS mapping. Hopefully we can abstract
some of that in the APMT code rather than expose it all to the PMU
driver...
Robin.
