On Thu, Feb 13, 2020 at 07:15:55PM +0100, Thierry Reding wrote: > On Thu, Feb 13, 2020 at 05:23:23PM +0000, Robin Murphy wrote: > > [+ Maxime] > > > > On 13/02/2020 4:39 pm, Thierry Reding wrote: > > > From: Thierry Reding <treding@xxxxxxxxxx> > > > > > > Hi, > > > > > > this set of patches adds a new binding that allows device tree nodes to > > > explicitly define the DMA parent for a given device. This supplements > > > the existing interconnect bindings and is useful to disambiguate in the > > > case where a device has multiple paths to system memory. Beyond that it > > > can also be useful when there aren't any actual interconnect paths that > > > can be controlled, so in simple cases this can serve as a simpler > > > variant of interconnect paths. > > > > Isn't that still squarely the intent of the "dma-mem" binding, though? i.e. > > it's not meant to be a 'real' interconnect provider, but a very simple way > > to encode DMA parentage piggybacked onto a more general binding (with the > > *option* of being a full-blown interconnect if it wants to, but certainly no > > expectation). > > The way that this works on Tegra is that we want to describe multiple > interconnect paths. A typical device will have a read and a write memory > client, which can be separately "tuned". Both of these paths will target > system memory, so they would both technically be "dma-mem" paths. But > that would make it impossible to treat them separately elsewhere. > > So we could choose any of them to be the "dma-mem" path, but then we > need to be very careful about defining which one that is, so that > drivers know how to look them up, which is also not really desirable. > > One other things we could do is to duplicate one of the entries, so that > we'd have "read", "write" and "dma-mem" interconnect paths, with > "dma-mem" referencing the same path as "read" or "write". That doesn't > sound *too* bad, but it's still a bit of a hack. Having an explicit > description for this sounds much clearer and less error prone to me. IIRC the dmaengine binding allows to do that, so it would make sense to me to have the same thing allowed for interconnects. Maxime
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