On Wed, Dec 18, 2019 at 09:44:05PM +0300, Dmitry Osipenko wrote: > UART clock is divided using divisor values from DLM/DLL registers when > enable-bit is unset in clk register and clk's divider configuration isn't > taken onto account in this case. This doesn't cause any problems, but > let's add a check for the divider's enable-bit state, for consistency. > > Acked-by: Peter De Schrijver <pdeschrijver@xxxxxxxxxx> > Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx> > --- > drivers/clk/tegra/clk-divider.c | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) All three patches applied to for-5.6/clk, thanks. Thierry
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