On Mon, Nov 11, 2019 at 04:32:35PM -0600, Bjorn Helgaas wrote: > On Mon, Nov 11, 2019 at 11:31:18AM +0530, Vidya Sagar wrote: > > On 11/6/2019 10:11 PM, Bjorn Helgaas wrote: > > > > Based on Vidya's backtrace, I think the resume path with problems > > > is this: > > > > > > pci_pm_resume_noirq > > > pci_pm_default_resume_early > > > pci_power_up > > > if (platform_pci_power_manageable(dev)) > > > platform_pci_set_power_state(dev, PCI_D0) # <-- FW delay here? > > > pci_raw_set_power_state > > > pci_update_current_state > > > pci_device_is_present # <-- config read returns CRS > > > > > > So I think your suggestion is that Vidya's firmware should be > > > doing the delay inside platform_pci_set_power_state()? > > > > > > Vidya, you typically work on Tegra, so I assume this is on an > > > arm64 system? Does it have ACPI? Do you have access to the > > > firmware developers to ask about who they expect to do the delays? > > > > Yes. This is on arm64 (Tegra) and we don't have any ACPI or any > > other firmware for that matter. PCIe is brought up directly in the > > kernel. > > I assume that your device is coming out of D3cold because apparently > you're seeing a CRS status from the config read when > pci_update_current_state() calls pci_device_is_present(). CRS status > should only happen after reset or power-on from D3cold, and you're not > doing a reset. > > I'm pretty sure platform_pci_power_manageable() returns false on > your system (can you confirm that?) because the only scenarios with > platform power management are MID (Intel platform) and ACPI (which you > don't have). > > Maybe you have some other platform-specific mechanism that controls > power to PCI devices, and it's not integrated into the > platform_pci_*() framework? My understanding after reading the PCIe specification is that CRS is a mechanism that allows an endpoint to signal that it isn't ready yet for operation after reset or power-on from D3cold. There's nothing in there that's platform specific. This is really only for specific endpoints. I don't see how adding platform specific PM code would help in this case. At a platform level we don't know if users are going to plug in a PCI endpoint that needs a long delay before it's ready after reset and/ or exit from D3cold. I do understand that perhaps pci_device_is_present() is perhaps not the best place to do complex CRS handling, but if a mechanism is clearly described in the specification, isn't it something that should be dealt with in the core? That way we don't have to quirk this for every device and platform. The PCIe specification says that: Software that intends to take advantage of this mechanism must ensure that the first access made to a device following a valid reset condition is a Configuration Read Request accessing both bytes of the Vendor ID field in the device's Configuration Space header. So doesn't that mean that pci_device_is_present() is already much too late because we've potentially made other configuration read requests in the meantime? Wouldn't it make more sense to push the CRS handling up a bit? The existing pci_power_up() function seems like it would be a good place. For example, adding code to deal with CRS right after the platform PCI PM calls but before pci_raw_set_power_state() seems like it would fit the restrictions given in the above quote from the specification. Thierry
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