On Mon, Sep 09, 2019 at 02:36:27PM +0200, Thierry Reding wrote: > From: Thierry Reding <treding@xxxxxxxxxx> > > The address width of the controller can be read from hardware feature > registers much like on XGMAC. Add support for parsing the ADDR64 field > so that the DMA mask can be set accordingly. > > This avoids getting swiotlb involved for DMA on Tegra186 and later. > > Also make sure that the upper 32 bits of the DMA address are written to > the DMA descriptors when enhanced addressing mode is used. > > Signed-off-by: Thierry Reding <treding@xxxxxxxxxx> > --- > drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 1 + > .../ethernet/stmicro/stmmac/dwmac4_descs.c | 4 ++-- > .../net/ethernet/stmicro/stmmac/dwmac4_dma.c | 20 +++++++++++++++++++ > .../net/ethernet/stmicro/stmmac/dwmac4_dma.h | 1 + > 4 files changed, 24 insertions(+), 2 deletions(-) I just ran into a case where this is not enough. The problem is that the driver not only doesn't fill in the upper 32 bits of the DMA address in the descriptors, it also doesn't program the upper 32 bits of the DMA address of the descriptors when initializing the channels. I'll update the patch for that case as well. Thierry
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