On 13/06/2019 10:47, Sameer Pujar wrote:
>
> On 6/13/2019 3:12 PM, Jon Hunter wrote:
>> On 13/06/2019 10:10, Sameer Pujar wrote:
>>> Add DT nodes for following devices on Tegra186 and Tegra194
>>> * ACONNECT
>>> * ADMA
>>> * AGIC
>>>
>>> Signed-off-by: Sameer Pujar <spujar@xxxxxxxxxx>
>>> ---
>>> changes in current revision
>>> * use single address range for all APE modules
>>> * fix address range for agic
>>>
>>> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 67
>>> ++++++++++++++++++++++++++++++++
>>> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 67
>>> ++++++++++++++++++++++++++++++++
>>> 2 files changed, 134 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>>> b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>>> index 426ac0b..b4d735e 100644
>>> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>>> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>>> @@ -1295,4 +1295,71 @@
>>> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>>> interrupt-parent = <&gic>;
>>> };
>>> +
>>> + aconnect@2a41000 {
>> This address does not look correct. This appears to be the address of
>> the AGIC. I think it should be 2900000, however, I also wonder if we
>> should even bother with an address for the aconnect as this is just a
>> bus and we don't specific a 'reg' property.
> Do you mean, should be ok to just mention "aconnect {"?
I did a bit more reading and for Tegra186 there are no registers
implement for the aconnect (which is different from Tegra210) and so in
this case we should just have ...
aconnect {
...
>>
>>> + compatible = "nvidia,tegra210-aconnect";
>>> + clocks = <&bpmp TEGRA186_CLK_APE>,
>>> + <&bpmp TEGRA186_CLK_APB2APE>;
>>> + clock-names = "ape", "apb2ape";
>>> + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges = <0x02900000 0x0 0x02900000 0x1FFFFF>;
>> This should be 0x1fffff.
> done
Sorry this should be 0x200000.
Cheers
Jon
--
nvpublic
