Quoting Joseph Lo (2018-12-18 01:12:18) > The CVB table contains calibration data for the CPU DFLL based on > process characterization. The regulator step and offset parameters depend > on the regulator supplying vdd-cpu, not on the specific Tegra SKU. > > When using a PWM controlled regulator, the voltage step and offset are > determined by the regulator type in use. This is specified in DT. When > using an I2C controlled regulator, we can retrieve them from CPU regulator > Then pass this information to the CVB table calculation function. > > Based on the work done of "Peter De Schrijver <pdeschrijver@xxxxxxxxxx>" > and "Alex Frid <afrid@xxxxxxxxxx>". > > Signed-off-by: Joseph Lo <josephl@xxxxxxxxxx> > --- Acked-by: Stephen Boyd <sboyd@xxxxxxxxxx>
