Re: [PATCH V3 05/20] clk: tegra: dfll: registration for multiple SoCs

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



Quoting Joseph Lo (2018-12-18 01:12:17)
> From: Peter De Schrijver <pdeschrijver@xxxxxxxxxx>
> 
> In a future patch, support for the DFLL in Tegra210 will be introduced.
> This requires support for more than 1 set of CVB and CPU max frequency
> tables.
> 
> Signed-off-by: Peter De Schrijver <pdeschrijver@xxxxxxxxxx>
> Signed-off-by: Joseph Lo <josephl@xxxxxxxxxx>
> Acked-by: Jon Hunter <jonathanh@xxxxxxxxxx>
> ---

Acked-by: Stephen Boyd <sboyd@xxxxxxxxxx>





[Index of Archives]     [ARM Kernel]     [Linux ARM]     [Linux ARM MSM]     [Linux USB Devel]     [Video for Linux]     [Linux Audio Users]     [Yosemite News]     [Linux Kernel]     [Linux SCSI]

  Powered by Linux