Re: [PATCH V2] clk: tegra: Return the exact clock rate from clk_round_rate

[Thierry Reding <thierry.reding@xxxxxxxxx>]

On Tue, Sep 25, 2018 at 05:49:40PM -0400, Robert Yang wrote:
> The current behavior is that clk_round_rate would return the same clock
> rate passed to it for valid PLL configurations. This change will return
> the exact rate the PLL will provide in accordance with clk API.
> 
> Signed-off-by: Robert Yang <decatf@xxxxxxxxx>
> ---
> Changes in V2:
>  - Move input divider (m == 0) check into the cfg constraints check
>    condition. Forgo adding WARN_ON and avoid using 0 input divider
>    all together.
> 
>  drivers/clk/tegra/clk-pll.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)

Acked-by: Thierry Reding <treding@xxxxxxxxxx>

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