On 17.10.2018 1:47, Stephen Boyd wrote: > Quoting Robert Yang (2018-09-25 14:49:40) >> The current behavior is that clk_round_rate would return the same clock >> rate passed to it for valid PLL configurations. This change will return >> the exact rate the PLL will provide in accordance with clk API. >> >> Signed-off-by: Robert Yang <decatf@xxxxxxxxx> >> --- > > I'm waiting for someone from Nvidia/Tegra background to review this > change. > Apparently Peter is taking a pause. I think Thierry's ACK to V1 should be still valid here. Also, if this helps: Reviewed-by: Dmitry Osipenko <digetx@xxxxxxxxx> Tested-by: Dmitry Osipenko <digetx@xxxxxxxxx>
