On Thu, Sep 27, 2018 at 10:32:03AM +0800, Joseph Lo wrote:
> Fix some incorrect data in LVL2 offset and bit mask.
>
> Fixes: e403d0057343 ("clk: tegra: MBIST work around for Tegra210")
> Signed-off-by: Joseph Lo <josephl@xxxxxxxxxx>
> Signed-off-by: Peter De Schrijver <pdeschrijver@xxxxxxxxxx>
> Acked-by: Jon Hunter <jonathanh@xxxxxxxxxx>
Acked-by: Peter De Schrijver <pdeschrijver@xxxxxxxxxx>
> ---
> V2:
> Add "Fixes" tag.
> ---
> drivers/clk/tegra/clk-tegra210.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> index 9eb1cb14fce1..290f7cb6a051 100644
> --- a/drivers/clk/tegra/clk-tegra210.c
> +++ b/drivers/clk/tegra/clk-tegra210.c
> @@ -2603,7 +2603,7 @@ static struct tegra210_domain_mbist_war tegra210_pg_mbist_war[] = {
> [TEGRA_POWERGATE_MPE] = {
> .handle_lvl2_ovr = tegra210_generic_mbist_war,
> .lvl2_offset = LVL2_CLK_GATE_OVRE,
> - .lvl2_mask = BIT(2),
> + .lvl2_mask = BIT(29),
> },
> [TEGRA_POWERGATE_SOR] = {
> .handle_lvl2_ovr = tegra210_generic_mbist_war,
> @@ -2654,14 +2654,14 @@ static struct tegra210_domain_mbist_war tegra210_pg_mbist_war[] = {
> .num_clks = ARRAY_SIZE(nvdec_slcg_clkids),
> .clk_init_data = nvdec_slcg_clkids,
> .handle_lvl2_ovr = tegra210_generic_mbist_war,
> - .lvl2_offset = LVL2_CLK_GATE_OVRC,
> + .lvl2_offset = LVL2_CLK_GATE_OVRE,
> .lvl2_mask = BIT(9) | BIT(31),
> },
> [TEGRA_POWERGATE_NVJPG] = {
> .num_clks = ARRAY_SIZE(nvjpg_slcg_clkids),
> .clk_init_data = nvjpg_slcg_clkids,
> .handle_lvl2_ovr = tegra210_generic_mbist_war,
> - .lvl2_offset = LVL2_CLK_GATE_OVRC,
> + .lvl2_offset = LVL2_CLK_GATE_OVRE,
> .lvl2_mask = BIT(9) | BIT(31),
> },
> [TEGRA_POWERGATE_AUD] = {
> --
> 2.19.0
>
