Re: [PATCH] soc/tegra: pmc: Add sysfs entry to get reset info

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On 25/09/2018 21.14, Thierry Reding wrote:
On Tue, Sep 25, 2018 at 04:52:46PM +0530, Sandipan Patra wrote:
1. Implementation of:
       tegra_pmc_get_system_reset_reason and
       tegra_pmc_get_system_reset_level
    These APIs provide information about tegra reset reason and level
    respectively.

2. sysfs entries:
      /sys/devices/platform/<address>.pmc/tegra_reset_reason and
      /sys/devices/platform/<address>.pmc/tegra_reset_level
    are implemented in readonly mode to fetch tegra reset reason and
    tegra reset level information.

Signed-off-by: Sandipan Patra <spatra@xxxxxxxxxx>
---
  drivers/soc/tegra/pmc.c | 132 +++++++++++++++++++++++++++++++++++++++++++++++-
  1 file changed, 131 insertions(+), 1 deletion(-)

Hi Sandipan,

Overall I think this is pretty nice. We've never had a use for checking
the reset reason before, so could you detail (in the commit message) how
you intend this to be used?

diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index ab719fa..ac74fee 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -2,6 +2,7 @@
   * drivers/soc/tegra/pmc.c
   *
   * Copyright (c) 2010 Google, Inc
+ * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
   *
   * Author:
   *	Colin Cross <ccross@xxxxxxxxxx>
@@ -92,7 +93,8 @@
  #define  PMC_SENSOR_CTRL_SCRATCH_WRITE	BIT(2)
  #define  PMC_SENSOR_CTRL_ENABLE_RST	BIT(1)
-#define PMC_RST_STATUS 0x1b4
+#define  PMC_RST_STATUS_T30		0x1b4

What about Tegra20? We've always used PMC_RST_STATUS on all generations,
so I would expect PMC_RST_STATUS_T30 to actually still work on Tegra20?

I checked the Tegra20 TRM and I didn't see the RST_STATUS register there in PMC (starting from Tegra30 it is there). I did see some reset status related stuff in CAR though so maybe it was moved (and changed) from CAR to PMC between Tegra20 and Tegra30?

Another option of course is that it's simply not documented in the TRM..

Cheers,
Mikko



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