Re: [RFC] drm/tegra: Add a flag to mark that there is only one display pll

[Dmitry Osipenko <digetx@xxxxxxxxx>]

On 9/5/18 12:37 PM, Peter De Schrijver wrote:
> > > Sorry, I had it wrong. It is 76Mhz. Not 72Mhz.
> > > I have spent a great deal of time trying to find alternate clock
> > > configuration for the display panel that can work. The only ways are:
> > >
> > >   - Run disp1 on pll_d
> > >   - Dedicate pll_c to disp1. Move all gpu clocks and sclk/hclk/ahbdma to pll_m.
> >
> > PLL_M is kinda reserved for the memory, hence its rate can't be changed.
>
> I think the best solution here would be to make use of the
> 'Assigned clock parents and rates' and rates feature to allow selecting the
> display clock sources on a per board basis.

Looks like it works, here the device-tree that I used:

	host1x@50000000 {
		dc@54200000 {
			clocks = <&tegra_car TEGRA20_CLK_DISP1>,
				 <&tegra_car TEGRA20_CLK_PLL_C>;

			/* Re-parent SCLK to P_OUT4 and set PLL_C to 586MHz */
			assigned-clocks = <&tegra_car TEGRA20_CLK_SCLK>,
					  <&tegra_car TEGRA20_CLK_HCLK>,
					  <&tegra_car TEGRA20_CLK_PCLK>,
					  <&tegra_car TEGRA20_CLK_PLL_C>;

			assigned-clock-rates = <216000000>, /* SCLK */
					       <216000000>, /* HCLK */
					       <54000000>,  /* PCLK */
					       <586000000>; /* PLL_C */

			assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_P_OUT4>;

			rgb {
				status = "okay";

				nvidia,panel = <&panel>;
			};
		};

		hdmi@54280000 {
			status = "okay";

			vdd-supply = <&hdmi_vdd_reg>;
			pll-supply = <&hdmi_pll_reg>;

			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
				GPIO_ACTIVE_HIGH>;
		};
	};