On Friday 24 August 2018 03:53:22 ryang wrote:
> There is a workaround in which the tegra rgb driver initializes
> the tegra dc pclk to 0 so that it will skip setting the parent clk rate.
>
> The relevant commits:
> 3cebae6737b100323baca21de6bce6647249e778
> 76d59ed049197bdaaa24c0e061a105af6ce74457
>
> A more recent commit sets the rate of the dc clk itself:
> 39e08affecf0998be1b01f4752016e33fa98eb9a
>
> This doesn't make sense because it always sets the dc clk to 0.
> Is this intended behavior or does it just happen to be working for
> the current tegra 2 boards in the mainline kernel?
>
>
> For context I am running the kernel on a tegra 2 based
> Galaxy Tab 10.1. The display panel driver is out of tree.
> This panel has very low clock rate tolerances so it must be
> driven at a rate very close to the required specification (68.75Mhz).
> pll_p is not adequate to drive this panel so pll_d must be used.
>
> Another issue is the current workaround is always forcing the disp1
> clk to zero. The Galaxy Tab 10.1 locks up completely when calling
> clk_set_rate with a clk rate of 0 whether the parent is pll_p or
> pll_d.
>
>
> This patch adds a flag single_display_pll to mark that the device has
> only one display pll. This replaces the the pclk = 0 workaround.
>
> There is a comment in rgb.c about using the shift clock divider for
> tegra 2 but the divider is not set due to the has_nvdisplay flag.
> This patch also sets the shift clock divider based on the
> single_display_pll flag.
>
> A change I'm uncertain about. In tegra_dc_commit_state()
> the dc clock is now being set to the display panel rate rather than zero.
>
> I don't have any other tegra devices to test with. So I don't know
> if this breaks other devices. Previously the code was trying to set the
> clock rate to zero anyways.
>
> Signed-off-by: ryang <decatf@xxxxxxxxx>
> ---
> drivers/gpu/drm/tegra/dc.c | 9 +++++++--
> drivers/gpu/drm/tegra/dc.h | 1 +
> drivers/gpu/drm/tegra/rgb.c | 1 -
> 3 files changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
> index 965088afcfad..03f1ad630254 100644
> --- a/drivers/gpu/drm/tegra/dc.c
> +++ b/drivers/gpu/drm/tegra/dc.c
> @@ -1664,7 +1664,7 @@ static void tegra_dc_commit_state(struct tegra_dc
> *dc, * which is shared with other peripherals. Changing the clock rate *
> should therefore be avoided.
> */
> - if (state->pclk > 0) {
> + if (!dc->soc->single_display_pll) {
We don't want to change pll_p rate here. It will be better to check whether
parent clock for disp is pll_d in tegra_rgb_encoder_atomic_check() and if it
is the parent, then allow to propagate pclk into commit_state. We may request
the pll_d using clk_get_sys(), then get the parent clock of disp by
clk_get_parent(disp_clk) and finally compare the parent with pll_d using
clk_is_math(parent, pll_d).
Certainly parent clock selection could be more advanced, ideally the best
parent clock should be selected in the atomic check and applied to disp clk
on the commit by changing the disp's parent. So pll_d could be always
selected if only one display controller is active at a time, otherwise the
atomic check should resolve the parent clocks based on the required rates. It
also could be permitable to adjust the pll_c rate.
