On Mon, Jul 30, 2018 at 03:04:46PM +0100, Jon Hunter wrote: > On 30/07/18 11:18, Mark Brown wrote: > > DSP modes only care about the rising edge of the LRCLK, the pulse can be > > any width without causing interoperability problems. > OK, thanks I was not able to find a spec that defines this, but I saw a > lot of codecs use a single bit clock width. So then equally making the > default '1' should also be fine. There's not really a spec for this, it's just what tends to be implemented. > I still do not like configuring the fsync width in this function. The > fsync width needs to be configured for both DSP modes and normal I2S > modes and so it seems it would be more appropriate to do this in the > hw_params function for this driver. You *could* just always use the I2S width, it's going to look odd when people use a scope but it will work most of the time.
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