Re: Tegra 2: Spurious interrupts from UARTA (@70006000)

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Hello Mikko!

On 06/18/2018 09:41 AM, Mikko Perttunen wrote:
> There seems to be an issue where if the receive interrupt is enabled
> when the receive queue is emptied, the interrupt status register will
> get updated but the actual interrupt line may not update. This can be
> worked around by disabling the receive interrupt in IER and then
> restoring the desired value to IER. In some downstream code, this is
> done in the IRQ handler when we detect a spurious interrupt, but
> presumably it could be done elsewhere as well.
> 
> David, can you try if doing that fixes the issue?

Actually I don't think this would help here, as it seems to be the *TX*
queue being the culprit. But I will give it a try shortly.

Also I might have found something helpful last friday. Testing over the
weekend shows promising results: no spurious interrupts.
It does NOT involve the wrongly muxed LPW2 though.

As I wrote earlier, the error occurs in the following sequence, when we
want to write something to the serial port:

 * when the TX queue is empty:
 * UARTA.IER := 0x15. Enable RHR (received data), RXS (receiver line
   status) and RX_TIMEOUT interrupts.

 * we want to write a character -> enable int. for an empty TX queue:
 * UARTA.IER := 0x17. Enable THR (transmitter holding reg. empty) Int.

 * we get an interrupt, as the queue has been empty for a while:
 * UARTA.IIR == 0xC2

 * now we write the char (in interrupt context)
 * UARTA.TX := some char

<<< added FIX:
  still in ISR, before writing 0x15, another write is added that
  also disables the ELSI interrupt:
  UARTA.IER := 0x11
  this seems to reliably shut down the spurious interrupt.
  Note that double-writing 0x15 here did not help. So this
  seems to relate to the RXS receiver line status interrupt.
<<< end of FIX.

 * still in ISR, kernel-side tx queue is empty, so disable:
 * UARTA.IER := 0x15.

 * WITHOUT above write, interrupt would be retriggered again, with:
 * UARTA.IIR == 0xC1

Currently this seems a bit like another silicon bug, where maybe the
interrupt line of the RXS interrupt is in a metastable state, and
disabling and re-enabling it properly resets to a valid state.

When I have sufficiently tested I will provide a proper patch for review
and hopefully some further context.

If you already have some comment on this, I'd be glad to hear it!

David
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