Hi Stefan, On Thu, 31 May 2018 11:37:41 +0200, Stefan Agner <stefan@xxxxxxxx> wrote: > On 27.05.2018 23:54, Stefan Agner wrote: > > Add support for the NAND flash controller found on NVIDIA > > Tegra 2 SoCs. This implementation does not make use of the > > command queue feature. Regular operations/data transfers are > > done in PIO mode. Page read/writes with hardware ECC make > > use of the DMA for data transfer. > > > > Signed-off-by: Lucas Stach <dev@xxxxxxxxxx> > > Signed-off-by: Stefan Agner <stefan@xxxxxxxx> > > --- > > MAINTAINERS | 7 + > > drivers/mtd/nand/raw/Kconfig | 6 + > > drivers/mtd/nand/raw/Makefile | 1 + > > drivers/mtd/nand/raw/tegra_nand.c | 999 ++++++++++++++++++++++++++++++ > > 4 files changed, 1013 insertions(+) > > create mode 100644 drivers/mtd/nand/raw/tegra_nand.c > > > [...] > > + > > + chip->ecc.read_page = tegra_nand_read_page_hwecc; > > + chip->ecc.write_page = tegra_nand_write_page_hwecc; > > + /* Not functional for unknown reason... > > + chip->ecc.read_page_raw = tegra_nand_read_page; > > + chip->ecc.write_page_raw = tegra_nand_write_page; > > + */ > > I am giving up on these raw read/write_page functions. Using DMA without > HW ECC just seems not to work. [...] > Note that the default implementations nand_(read|write)_page_raw which > use exec_op do work fine! Unfortunately, the PIO mode only allows 4 > bytes in a read cycle, hence raw read/write is slow... > Well, if raw accessors work in PIO mode, I suppose it's not a big deal. Thanks for trying anyway! Miquèl -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
